1. Field of the Invention
The present invention relates to a semiconductor apparatus and method of manufacturing the same. More particularly, the present invention relates to a structure of silicon bipolar junction transistor used for high frequency grounded emitter amplification and a structure of a silicon field effect transistor used for high frequency grounded source amplification, and a method of manufacturing the transistors.
2. Description of Related Art
To develop high frequency radio communication technology, it is essential for an amplifier technology used in communication devices to develop. An amplifier for high frequency radio communication is desired to further increase an output from communication wave of higher frequency range.
Semiconductor devices formed by compound semiconductor is used to amplifiers in a conventional high frequency radio communication technology. However to form a semiconductor device using compound semiconductor, expensive substrate material is needed with a complicated manufacturing process, thereby rising price of the semiconductor device formed by compound semiconductor. Accordingly an amplifier using semiconductor device formed of cheap silicon is required.
A technology to make a substrate conductive with an emitter as a BJT (Bipolar Junction Transistor) designed for high gain used in a conventional high frequency radio communication technology is disclosed (for example in Japanese Unexamined Patent Application Publication No. 2004-128142). FIG. 22 shows a plan layout view showing each electrode and line of a sub-emitter BJT 90 aiming for high gain according to a conventional technique. FIG. 23 is a cross-sectional diagram taken along the line XXIII-XXIII of FIG. 22 according to a conventional technique.
In the sub-emitter BJT 90, a high resistance p− type epi 902 is formed on a low resistance p+ type substrate 901. In a device forming region inside the high resistance p− type epi 902, a highly concentrated and low resistance n+ type buried layer 903 is formed to be a collector. A high resistance n− type epi 904 is formed on the high resistance p− type epi 902.
In regions other than the device forming region for the p− type epi, a highly concentrated and low resistance p+ type buried layer 909 is mounted. A highly concentrated and low resistance p+ type sub-emitter layer 910 is mounted to the n− type epi 904 above the p+ type buried layer 909. The p+ type buried layer 909 is formed to penetrate the p+ type epi 902. The p+ type sub-emitter layer 910 is formed to penetrate the n− type epi 904.
Further, a p type base layer 905 is formed on the n− type epi 904 above the n+ type buried layer 903. An n+ type emitter layer 907 is formed on the p type base layer 905. On the n− type epi 904, an n+ type epi 908 collector layer with its bottom reaching to the n+ type buried layer 903 is formed.
A base electrode B, an emitter electrode E, and a collector electrode C are formed via openings provided in an insulator film 911 respectively on the p type base layer 905, the n+ type emitter layer 907, and the n+ type contact layer 908.
The emitter electrode E is connected with a sub-emitter electrode SE by an electrode line. The emitter electrode E is conductive with the low resistance p+ type substrate 901 via the sub-emitter electrode SE, a p+ type buried layer 909 and a p+ type sub-emitter layer 910. A metal layer 925 is deposited on a back side of the low resistance p+ type substrate 901.
A chip of the conventional sub-emitter BJT 90 arranged as described in the foregoing is mounted on an island of a lead frame using the metal layer 925 mentioned above as well as electrically connected with the island.
Although not shown in FIG. 17, a collector bonding pad CP and a base bonding pad BP shown in FIG. 18 are electrically connected to a lead of a lead frame by a bonding wire.
The sub-emitter BJT 90 formed as described in the foregoing is electrically connected to an emitter lead frame using the metal layer 925 on the back side of the chip, thereby not requiring the bonding wire to connect to the emitter lead. Therefore, an inductance caused by the bonding wire is completely eliminated, so that a high frequency power gain when amplifying grounded emitter (2 to 4 dB improvement in 0 to 8 GHz).
Further, in the sub-emitter BJT 90 of a conventional technique, as the low resistance p+ type sub-emitter layer 910 provided to the p− type epi 902 and the n− type epi 904 is placed below a bonding pad 924, the p+ type sub-emitter layer 910 is connected to ground via a back side of a chip.
It is therefore possible to suppress thermal noise generated due to resistance in the epi layer from entering into the base electrode through parasitic capacitance in an insulator film placed below the base bonding pad BP. Accordingly noise of the sub-emitter BJT can be reduced (i.e. The NF of the sub-emitter BJT can be reduced).
To attempt to increase an output of a semiconductor device using a high gain characteristic of a sub-emitter structure, unit devices in the sub-emitter structure are connected in parallel to form multi-cell so as to expand an emitter area. If each unit device behaves unequally, a thermal runaway could occur as the sub-emitter region is not separated by each unit device.
Further, in the BJT having a sub-emitter structure, a positive correlation exists between an emitter current and a device temperature. That is, if the temperature increases, the emitter current also increases, and if the emitter current increases, the temperature further increases, inducing a vicious cycle. Therefore, the devices may be destroyed due to the thermal runaway and it is impossible to have a stable high output operation with a structure in which unit devices of a sub-emitter structure being connected in parallel to form multi-cell.